EDI8F81025C 1megx8 sram module 1 EDI8F81025C rev. 5.0 6/96 eco#7549 1megx8 static ram cmos, module the EDI8F81025C is an 8 megabit cmos static ram based on two 512kx8 static rams mounted on a multi- layered epoxy laminate (fr4) substrate. a low power version with data retention (edi8f81025lp) is also available. all inputs and outputs are ttl compatible and operate from a single 5v supply. fully asynchronous, the EDI8F81025C requires no clocks or refreshing for operation. features 1 meg x 8 bit cmos static random access memory ? access times 70 thru 100ns ? data retention function (edi8f81025lp ) ? ttl compatible inputs and outputs ? fully static, no clocks high density packaging ? 36 pin dip, no. 180 single +5v ( 10%) supply operation pin configurations and block diagram vcc nc nc a15 a17 w a13 a8 a9 a11 g a10 e dq7 dq6 dq5 dq4 dq3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 nc a19 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a dq dq1 dq2 vss 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 pin names pin names a?-a19 address inputs e chip enable w write enable g output enable dq?-dq7 common data input/output vcc power (+5v 10%) vss ground nc no connection a -a18 w g a19 e decoder dq -dq7 electronic designs incorporated ? one research drive ? westborough, ma 01581usa ? 508-366-5151 ? fax 508-836-4850 ? electronic designs europe ltd. ? shelley house, the avenue ? lightwater, surrey gu18 5rf united kingdom ? 01276 472637 ? fax: 01276 473748
EDI8F81025C 1megx8 sram module 2 EDI8F81025C rev. 5.0 6/96 eco#7549 absolute maximum ratings* recommended dc operating conditions dc electrical characteristics parameter sym conditions min typ* max units operating power icc1 w, e = vil, ii/o = 0ma, -- 100 140 ma supply current min cycle standby (ttl) power icc2 e 3 vih, vin vil -- 25 55 ma supply current vin 3 vih full standby power icc3 e 3 vcc-0.2v c -- 1.5 2 ma supply current (cmos) vin 3 vcc-0.2v or lp -- 200 300 m a vin 0.2v input leakage current ili vin = 0v to vcc -10 -- 10 m a output leakage current ilo v i/o = 0v to vcc -10 -- 10 m a output high voltage voh ioh =-1.0ma 2.4 -- -- v output low voltage vol iol = 2.1ma -- -- 0.4 v *typical: ta = 25 c, vcc = 5.0v capacitance truth table (f=1.0mhz, vin=vcc or vss) parameter sym max unit ac test conditions parameter sym min typ max units iinput pulse levels vss to 3.0v input rise and fall times 5ns input and output timing levels 1.5v output load 1ttl, cl =100pf (note: for tehqz,tghqz and twlqz, cl = 5pf) g e w mode output power x h x standby high z icc2, icc3 h l h output deselect high z icc1 l l h read dout icc1 x l l write din icc1 supply voltage vcc 4.5 5.0 5.5 v supply voltage vss 0 0 0 v input high voltage vih 2.2 -- 6.0 v input low voltage vil -0.3 -- 0.8 v address lines ci 30 pf data lines cd/q 43 pf chip enable line cc 10 pf write and output enable lines cw 32 pf these parameters are sampled, not 100% tested. voltage on any pin relative to vss -0.5v to 7.0v operating temperature ta (ambient) commercial 0 c to +70 c industrial -40 c to +85 c storage temperature -55 c to +125 c power dissipation 1 watt output current. 20 ma *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability.
EDI8F81025C 1megx8 sram module 3 EDI8F81025C rev. 5.0 6/96 eco#7549 ac characteristics read cycle symbol 70ns 85ns 100ns parameter jedec alt. min max min max min max units read cycle time tavav trc 70 85 100 ns address access time tavqv taa 70 85 100 ns chip enable access time telqv tacs 70 85 100 ns chip enable to output in low z (1) telqx tclz 5 5 5 ns chip disable to output in high z (1) tehqz tchz 30 35 40 ns output hold from address change tavqx toh 5 5 5 ns output enable to output valid tglqv toe 40 45 50 ns output enable to output in low z (1) tglqx tolz 5 5 5 ns output disable to output in high z(1) tghqz tohz 30 35 40 ns note 1: parameter guaranteed, but not tested. tghqz telqv telqx e g q tehqz a tavav tglqv tglqx tavqv tavav tavqv tavqx data 2 a q address 1 address 2 data 1 read cycle 1 - w high, g, e low read cycle 2 - w high
EDI8F81025C 1megx8 sram module 4 EDI8F81025C rev. 5.0 6/96 eco#7549 ac characteristics write cycle note 1: parameter guaranteed, but not tested. write cycle symbol 70ns 85ns 100ns parameter jedec alt. min max min max min max units write cycle time tavav twc 70 85 100 ns chip enable to end of write telwh tcw 65 70 80 ns teleh tcw 65 70 80 ns address setup time tavwl tas 0 0 0 ns tavel tas 0 0 0 ns address valid to end of write tavwh taw 65 70 80 ns taveh taw 65 70 80 ns write pulse width twlwh twp 65 70 80 ns twleh twp 65 70 80 ns write recovery time twhax twr 5 5 5 ns tehax twr 5 5 5 ns data hold time twhdx tdh 0 0 0 ns tehdx tdh 0 0 0 ns write to output in high z (1) twlqz twhz 0 30 0 35 0 40 ns data to write time tdvwh tdw 30 35 40 ns tdveh tdw 30 35 40 ns output active from end of write (1) twhqx twlz 5 5 5 ns write cycle 1 - w controlled a e w d q tavav telwh tavwh twlwh tavwl tdvwh twhdx twhqx high z twlqz data valid twhax
EDI8F81025C 1megx8 sram module 5 EDI8F81025C rev. 5.0 6/96 eco#7549 a w e d q tavav tavel tehax tdveh tehdx teleh taveh data valid high z twleh write cycle 2 e controlled data retention mode e 3 vdd -0.2v e vcc tcdr tr 4.5v 4.5v vdd data retention - e controlled data retention characteristics lp version only characteristic sym test conditions vdd min typ max unit 70 c85 c data retention voltage vdd 2 -- -- -- v data retention quiescent current iccdr e 3 vdd -0.2v 2v -- 100 130 m a vin 3 vdd -0.2v 3v -- 160 210 m a chip disable to data retention time tcdr(1) or vin 0.2v 0 -- -- -- ns operation recovery time tr (1) tavav* -- -- -- ns note: parameter guaranteed, but not tested * read cycle time
EDI8F81025C 1megx8 sram module 6 EDI8F81025C rev. 5.0 6/96 eco#7549 electronic designs incorporated ? one research drive ? westborough, ma 01581usa ? 508-366-5151 ? fax 508-836-4850 ? electronic designs europe ltd. ? shelley house, the avenue ? lightwater, surrey gu18 5rf united kingdom ? 01276 472637 ? fax: 01276 473748 electronic designs inc. reserves the right to change specifications without notice. cage no. 66301 ordering information standard power low power speed package with data retention (ns) no. EDI8F81025C70b6c edi8f81025lp70b6c 70 180 EDI8F81025C85b6c edi8f81025lp85b6c 85 180 EDI8F81025C100b6c edi8f81025lp100b6c 100 180 package no. 180 36 pin dual-in-line package package description 2.010 max 0.670 max 0.620 0.590 17 x 0.100 1.700 ref. 0.100 typ 0.150 ref 0.175 0.125 0.220 max note: to order an industrial grade product substitute the letter c in the suffix with the letter i, eg. EDI8F81025C70b6c becomes EDI8F81025C70b6i.
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